The present invention relates to a semiconductor memory device of and process for producing the same, and more particulary, to a mask ROM device having NAND type high integration double polycrystalline silicon and process for producing the same.
A Mask ROM (Mask Read Only Memory) is a read only memory device that is unable to change data after the data is fixed in a process for producing elements. However, since the structure of a cell is simple, the degree of integration is the highest among semiconductor memory devices, and the same data can be simultaneously programmed to a plurality of semiconductor devices in the case of manufacturing elements, which can be programmed at little expense, thereby creating an advantage in the pricing of elements.
The method of programming mask ROM is generally divided into two steps, one of which is that a manufacturer determines the data previously, and another is that data is programmed by the designation of a user. In the case where data is programmed by the designation of a user as aforementioned, after the process is executed just prior to the process for programming and the data is programmed according to the order of a user, the elements are manufactured by executing the remaining process.
Recently, a cheap mask ROM of a large capacity has become required due to the tendency to make the character font of high resolution and high sound quality in OA instruments, electronic musical instruments, and TV games. In response to the tendency to produce high integration semiconductor devices as described previously, U.S. Pat. No. 4,142,176 proposes a mask ROM device having a NAND cell (hereinafter called as a memory string). The equivalent circuit of said memory string is shown in FIG. 1, and a memory cell array is organized with a plurity of memory strings arranged by a matrix system in rows and columns. Said memory string MS is organized with a string selection transistor ST connected to a bit line that the drain corresponds thereto, and MOS transistors MC1-MC8 of 8 bits have drain-source paths serially connected between the source of said string selection transistor ST and the ground line. In addition, the gates of the string selection transistors ST and the gates of the MOS transistors MC1-MC8 are connected respectively with the string selection line SSL and the word lines WL1-WL8 which are row lines parallel to each other.
Hereinafter, the reading operation of said NAND type mask ROM device will be described with reference to FIG. 1. It will be described by exemplifying that of programmed with fourth memory cell MC4 contained within memory string MS.
When a reading voltage of about 1-2V is applied to the selected bit line BL and the power source voltage VCC is applied to the selected string selection line SSL, the string selection transistor ST is "turned on". Furthermore, reading is accomplished by applying OV to the word line WL4 connected to the gate of the selected fourth memory cell MC4 and by applying the power source voltage VCC to word line connected to the gates of the remaining non-selected MOS transistors. That is, when the selected fourth memory cell MC4 is in enhancement-type, a reading voltage applied to the bit line BL is transferred through the "turned on" string selection transistor ST and memory cells MC1-MC3 to the drain of the fourth memory cell MC4. However, since the fourth memory cell MC 4 is in the "off" state, the "off" state is sensed by preventing that reading voltage applied to said bit line BL being discharged through the memory cells MC5-MC8 to the ground line. In case the fourth memory cell MC4 is in a depletion state, the reading voltage applied to said bit line BL is transferred through the "turned on" string selection transistor ST and the memory cells MC1-MC8 to the ground line whereby the "on" state is sensed.
FIG. 2 is a plan view of a memory string in a mask ROM having the conventional NAND cell. It will be easily understood that a memory array has a plurality of memory strings.
FIG. 3 shows a cross sectional view taken along the line a--a' of FIG. 2. The memory string MS has N+ diffusion regions 14, 16 separated by a channel region 17 on the surface of the P-type semiconductor substrate 10. The gate 20 is formed with polycrystalline silicon on the top portion of a gate oxide film 22 on said channel region 17.
A metal film 18 formed by aluminum and utilized into the bit line BL forms a contacting surface 12 by contacting the N+ diffusion region 14 through the opening formed on the top portion of the N+ diffusion region 14.
Furthermore, said N+ diffusion region 16 owns jointly with adjacent memory cells thereby becoming source and drain regions.
Returning to FIG. 2, the bit line BL made of the metal film 18 expanding in row is connected to the N+ diffusion region 14 formed within P-type semiconductor substrate 10 through the contacting opening 13. Said N+ diffusion region 14 is connected with the drain of the string selection transistor ST of the memory string MS.
The source of said string selection transistor ST is connected with the drain of the first memory cell MC1. Furthermore, the drain-source paths of the memory cells MC1-MC8 contained within the memory string MS is serially connected between the drain of said string selection transistor ST and the ground line. Oblique lined regions 15 are string section line SSL and the word lines WL1-WL8 formed with the polycrystalline silicon, wherein the regions crossing with the bit line BL are the gates of the string selection transistor ST and the memory cells MC1-MC8.
Since the NAND type mask ROM device as described above has a broad insulating area for isolating the memory cells serially connected through the diffusion layer to one memory string, there has been a problem of the setting limits for high integration of a memory cell array.